Due to the inevitable requirements to further shrink design rules while still maintaining sufficient oxide thickness for isolation, there is a trend in the semiconductor field away from Local Oxidation of Silicon (LOCOS) and toward Shallow Trench Isolation (STI) because STI has superior scalability. However, STI is not without its disadvantages.
FIG. 1 illustrates a conventional flash memory structure 100 using STI. Flash memory structure 100 has a plurality of bitlines 110 and a wordlines 120. A memory cell is formed by the intersection of a bitline and a wordline. In between the bitlines 110 are the STI trenches. Due to damage caused at the bitline-STI edge during manufacturing, current variations are seen at the bitline-STI edge. In other words, the current through the a bitline 110 has both a center current component 130 and an edge current component 140. The edge current component 140 is much slower than the center current component 130. The presence of the slower edge currents 140 causes increased programming time, thus limiting the programming speed of the memory cell. Consequently, conventional memory cells using STI technology achieve less than optimal programming speeds.